In early semiconductor integrated circuits, resistors were provided by diffused regions or by portions of a semiconductor substrate defined by etchings. As the density of components in integrated circuits grew, the area occupied by resistors became prohibitive, so logic forms were favored since they employed few or no resistors. For example, transistor-transistor logic (TTL) and integrated injection logic (I.sup.2 L) in bipolar technology had features minimizing the area on a bar dedicated to resistors. In metal-oxide semiconductor (MOS) logic and memories, transistors are used as load devices. Numerous examples of complex MOS circuits containing large numbers of transistors, but no resistors, in a single chip digital processor or memory chip are known in the art. For improved versatility, however, it is desirable to provide diffusion type resistors for such chips, particularly for dynamic random access memory (DRAM) chips and integrated DRAM/logic chips.
One element of concern in the formation of diffusion resistors for DRAM or DRAM/logic chips is that the number of additional mask steps required to fabricate the structures be limited, and preferably that no additional mask processing be necessary other than that already required for the formation of the DRAM chip or DRAM/logic chip itself. With each additional mask, complexity increases. For example, elements on a chip must align within a few microns, and masks which are aligned in one portion of a wafer with respect to a previous masking operation may be out of registry in another portion of the wafer. Thus, it is important to limit the number of masks required to provide the on-chip diffusion resistor structure.
As another consideration, refractory metals and refractory metal suicides have often been used for interconnecting conductive structures. These materials posses low resistivity characteristics normally associated with metals such as aluminum and copper without providing the manufacturing challenges inherent in those materials. Typically, silicide electrodes are formed on silicon diffusion regions by depositing the refractory metal layer on the substrate, heating the metal to form silicide regions over the exposed silicon region, and treating the substrate in a wet etchant to remove unreacted refractory metal. When applied over a diffusion resistor, the silicide forming method possesses problems in that the resistance of the resultant structure is too low to be of general use, and the resistance can vary considerably from site to site. Thus, the usefulness of such a structure as a resistor is highly questionable.
Commonly assigned U.S. Pat. No. 5,185,294, entitled "Boron Out-Diffused Surface Strap Process," the entirety of which is hereby incorporated herein by reference, describes one process of interest. In this patent, a novel process is described for strap formation in a semiconductor device to electrically connect a first silicon region to a second silicon region when the regions are separated by a dielectric. This patent addresses the need for forming a low resistance connection between conductive structures, but does not address the fabrication of diffusion resistors.
Accordingly, there exists a need in the art to provide semiconductor diffusion resistor structures with controlled resistivity and silicided contact areas, without necessarily having an increase in the number of masking steps required to fabricate a semiconductor chip incorporating the structures.